Appeal No. 94-3596
Application No. 07/689,655
the common path [68] so that devices [52] having cache
memories [190] can set flags to invalidate associated
cache-memory locations. In this way, devices [52]
having cache memories [190] can keep track of whether
their cache data are valid or invalid even when the
local memory [54] is accessed by way of the private
communications path [58] (column 4, lines 45 through
59).
The invalidation teachings of Bomba are not relevant to the
claimed suspension of instruction execution in a target
processor.
The obviousness rejection of claims 1, 2, 4, 6 through 11,
13, 14, 16, 17 and 20 is reversed because neither Vince nor Bomba
teaches or would have suggested the claimed suspension operation.
The obviousness rejection of claims 12, 15, 18 and 19 is
reversed because the teachings found in Vrielink and Gunter do
not cure the noted shortcomings in the teachings of Vince and
Bomba.
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