Appeal No. 95-0933
Application 08/032,764
application.
The invention relates generally to a computer designed to
parallel execute arithmetic and logical operations on packed
data. In particular, Appellants disclose on page 3 that
Figure 2
shows a diagram of three operands 210, 220 and 230 packed into
a single 32 bit word 200. Appellants further disclose that
the 32 bit word 200 includes buffer bits 240, 250 that are
placed between the operands.
Independent claims 1 is reproduced as follows:
1. Method of processing a plurality of multidigit
operands in parallel comprising the steps of:
a) packing the multidigit operands into a first
word with at least one buffer bit between each
multidigit operand; and
b) performing arithmetic operations on the first
packed word with a second word, thereby
providing a processed packed word.
The reference relied on by the Examiner is as follows:
Bertrand 4,963,867 Oct. 16, 1990
Claims 1 through 17 stand rejected under 35 U.S.C. § 102
2
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