Appeal No. 95-1123
Application 08/028,757
This is an appeal from the final rejection of claims
1-7, which constitute all the claims remaining in the
application.
Claim 1 reads as follows:
1. A pipelining processor comprising a plurality of
functional units and an instruction issuing unit operatively
connected thereto for issuing multiple instructions
concurrently and for allowing for the processing of
instructions in an out-of-order sequence, said instruction
issuing unit having means for handling an interrupt of said
processor to facilitate continued operation upon said out-of-
order instructions upon termination of said interrupt, said
pipelining processor further comprising an execution unit, and
said instruction issuing unit including an instruction window
and an instruction buffer, said instruction issuing unit being
operatively connected to said execution unit, said instruction
window being adapted to store a value representative of a
number of uncompleted instructions, so that when an interrupt
to said processor occurs, previously issued instructions that
have been interrupted and are hence uncompleted can be
executed by said execution unit, said value providing a
precise interrupt point for returning to an interrupted
program by defining a precise interrupt boundary as said group
of instructions in said instruction window.
The examiner’s answer cites the following prior art:
Acosta et al. (Acosta), “An Instruction Issuing Approach to
Enhancing Performance in Multiple Functional Unit Processors”,
IEEE Transactions on Computers, Vol. C-35, No. 9 (September
1986) pages 815-828.
Inagami et al. (Inagami) 4,782,441 Nov.
1, 1988
2
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