Appeal No. 95-2433
Application No. 08/076,080
disclose an arithmetic operation circuit, this does not
preclude the circuit, or part thereof, from operating in a
clamping circuit manner. It would appear that the signal at
the terminal OUT in Nagano is clamped to the voltage level
generated from Q4 by transistor Q3, just as appellant’s
transistor 132 clamps output 100 to the voltage generated by
transistor 135. This has been the examiner’s position and,
while that position appears quite reasonable to us, appellant
has provided no argument thereagainst, other than to say that
there is no clamping function in Nagano. Appellant has not
provided any argument or evidence as to why terminal OUT in
Nagano is not clamped to the voltage level generated from
transistor Q4 by transistor Q3.
We also note, as we did at page 5 of our decision, that
while appellant argues the “square-law clamping” aspect of the
invention, this term appears only in the claim preamble and
there is nothing within the body of the claim indicative of
any “square-law clamping” or any clamping at all.
With regard to appellant’s last argument relative to
current IO in Nagano, it is not seen where this argument is
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