Appeal No. 95-2599
Application 07/983,931
claims 6, 8 through 10, 22, 24 and 25. Claims 1 through 5, 7, 11
through 21 and 23 have been canceled.
The invention relates generally to a field effect
transistor. Appellants disclose on pages 3 and 4 of the
specification that N+ impurities are diffused in a transverse
direction producing an overlapping portion in a distance )L under
gate electrode 3 as shown in Figure 1C. This overlapping portion
constitutes an additional capacitance between the gate and the
source-drain preventing the transistor from operating at a high
speed as well as increasing the power consumption of the
transistor.
On page 9 of the specification, Appellants disclose that
they solved this problem by forming a field effect transistor
with a T-shaped gate electrode 3 having a lower layer 3a and an
upper layer 3b as shown in Figure 4A. On page 12 of the
specification, Appellants disclose that the lower layer 3a and
the upper layer 3b are etched by a known plasma etching method as
shown in Figure 5C. The lower layer 3a and the upper layer 3b
are formed of the same base composition, i.e. polysilicon.
However, Appellants disclose that these layers contain a
differing chemical or physical feature which provides the lower
layer 3a with a faster etch rate as compared with the upper layer
2
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