Appeal No. 95-3125
Application 08/071,920
a plurality of secondary hardware interfaces each having
a secondary HCMI;
data and control transmission line means parallel
connected to each of said HCMIs;
said CPU having means for transmitting and receiving data
and control bytes of information employed to control said
plurality of input/output devices;
said bytes of information comprising a data byte, an
error byte and an address/command byte which defines the
absence or presence of another data byte as well as the
address of the input/output device being addressed, and
a HCMI address counter in each said secondary HCMI which
defines the unique address of the secondary HCMI with which
the host HCMI is to communicate, whereby
said bytes of information communicated to or from said
CPU and an input/output device are active when the address
counter activates a unique secondary HCMI.
The examiner relies on the following reference:
Ketelhut et al. (Ketelhut) 4,764,868 Aug. 16, 1988
Claims 1-12 stand rejected under 35 U.S.C. § 103. As
evidence of obviousness the examiner offers Ketelhut taken
alone.
Rather than repeat the arguments of appellant or the
examiner, we make reference to the briefs and the answer for
the respective details thereof.
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