Appeal No. 95-4220
Application No. 08/176,297
The invention pertains to a method and apparatus for
estimating power in an integrated circuit.
Representative independent claim 5 is reproduced as
follows:
5. A computer implemented method for estimating power
dissipation characteristics of a circuit comprising a
plurality of nodes, the method used in a circuit design
process for designing an electronic circuit for operation at a
certain clock rate and having a first number of nodes and a
second number of gates, said method comprising the following
steps:
(a) analyzing predefined artwork data associated with
said circuit to determine data on the geometry of a first
node;
(b) generating capacitance data for said first node on
the basis of said geometry data;
(c) generating frequency data associated with said first
node;
(d) determining voltage data associated with said first
node;
(e) computing an estimate of power associated with said
first node on the basis of at least said capacitance,
frequency and voltage data;
(f) repeating the above steps for each remaining node;
(g) summing said estimates of power for each node to
determine an estimate of total power dissipation for the
circuit; and
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