Appeal No. 95-4603 Page 2
Application 08/101,641
equipment for logical circuitry. Claim 4 (emphasis added) is
representative of the claims on appeal:
4. A method for testing a digital circuit
device, said method comprising the steps of:
simulating test results, for a model of a
digital circuit to be tested, using simulated
test pattern bit streams generated in accordance
with a weighted, pseudo-random process having
selectable seed values;
determining from said simulating step which
seed values from a sequence of seed values
produce test results which are effective for
detecting error conditions in said digital
circuit;
storing, in a memory element, values which
are indicative of which seed values in said
sequence are to be skipped as a result of said
effectiveness determining step; and
applying a weighted, pseudo-random test
pattern bit stream to an actual digital circuit
device, said test pattern being generated using
a reduce seed sequence based upon said skipping
indicators in said memory element.
The examiner relied on the following references in
combination to reject all of all the pending claims under
35 U.S.C. § 103:
Jacobson 4,715,034 22 Dec. 1987
Eichelberger et al. (Eichelberger) 4,801,870 31 Jan. 1989
According to the examiner, Eichelberger teaches the subject
matter of the invention except for the seed-skipping function.
(Paper 4 at 4.) We take this finding as a given in reaching
our decision. The examiner finds that Jacobson inherently
teaches skipping ineffective seeds. (Paper 14 at 5.)
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