Appeal No. 96-0254
Application 08/096,149
Instead, Guttag teaches the summation of bits with a
logic level of “one” for a time interval between vertical sync
pulses (col. 49, lines 27-30), not the analysis of an individual
word. In addition, Guttag teaches away from appellant’s
invention by teaching a running total of the number of bits with
a logic level of “one” (col. 49, lines 48-55), which sums for the
entire data string, not appellant’s analysis employing a word by
word test, in which a word is “captured” for analysis while the
rest of the data string is allowed to pass. When the data string
is repeated, the next word in the string is captured et cetera,
until all the words have been tested at a sampling rate which is
a fraction of the clock rate of the circuit under test.
Accordingly, since Guttag fails to teach or render
obvious the limitations of claim 8, we cannot sustain the
rejection of claims 8-12 under 35 U.S.C. § 103 as being
unpatentable over Guttag.
The decision of the examiner is reversed.
REVERSED
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