Appeal No. 96-0905
Application No. 08/116,950
This is a decision on appeal from the final rejection of
claims 1 through 8, 11 through 14 and 16 through 26, all of the
claims remaining in the application.
The invention is directed to a fault-tolerant computer
system employing multiple CPUs. Each CPU has its own independent
clock in order to avoid imposing the expense, complexity and
timing problems of typical fault-tolerant clocking. However, the
CPUs are loosely synchronized by detecting certain events and
stalling any CPU ahead of the others until all the CPUs execute
the required function simultaneously. Interrupts are also
synchronized to the CPUs in order that the CPUs all execute the
interrupt at the same point in the instruction stream which they
are all executing. More particularly, each of the CPUs has a
counter which counts machine cycles corresponding to execution
cycles but does not count stall cycles. Further, each CPU is
interrupted at some predetermined count value. All interrupts
are made to occur at the same virtual time in each CPU, though
not necessarily at the same point in real time.
Representative independent claim 1 is reproduced as follows:
1. A multiple CPU system, comprising:
a) a plurality of CPUs concurrently executing a same
instruction stream, the CPUs each being clocked
independently of one another to provide separate machine
2
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