Appeal No. 96-1621
Application No. 08/194,899
The invention pertains to a precoding and steering
mechanism for instructions in a superscaler processor.
Representative independent claim 19 is reproduced as
follows:
19. In a computing system, a method comprising the steps
of:
(a) fetching a first instruction from a main memory;
(b) fetching a second instruction and a third
instruction from main memory;
(c) predecoding the first, second and third instructions
to generate predecode bits, wherein the predecode bits include
bundling information which indicates whether execution of the
second instruction is to be bundled with execution of the
first instruction and which indicates whether the execution of
the second instruction is to be bundled with execution of the
third instruction and wherein the predecode bits additionally
include steering information which is in addition to the
bundling information, the steering information being used in
order to steer each of the first, second and third
instructions to one of a first integer arithmetic logic unit,
a second integer arithmetic logic unit and a floating point
unit for execution; and,
(d) storing the second and third instructions as a
double word in an instruction cache, the predecode bits being
stored along with the double word in the instruction cache.
The examiner relies on the following references:
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