Appeal No. 96-3244
Application No. 08/238,192
DECISION ON APPEAL
This is an appeal from the final rejection of claims 1,
2, 4, 6 through 9, 11 and 13. In a first Amendment After
Final (paper number 33), claim 8 was amended. Appellants’
second Amendment After Final (paper number 39) was not entered
by the examiner (paper number 40).
The disclosed invention relates to the testing of a
circuit.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. In a logic circuit having a plurality of output
control signals and a plurality of input/output signals, a
reset circuit comprising:
a first input means for receiving a reset signal having
an asserted state and a negated state;
a second input means for receiving a mode signal having
an asserted and a negated state; and
a circuit, coupled to receive said reset signal and said
mode signal, for generating a first control signal to force
each of said output control signals to a negated state and a
second control signal for causing said input/output signals to
be tristated, such that (i) when said reset signal is in said
asserted state and said mode signal is in said asserted state,
said first control signal is asserted to force each of said
output control signals to a negated state and said second
control signal is asserted to tristate said input/output
signals for as long as said mode signal is in said asserted
state, (ii) when said mode signal transitions from said
2
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