Appeal No. 96-3767
Application 07/970,260
event that the divisor is determined to be present in the cache
memory but not the dividend.” In accordance with the last
paragraph of column 2 of Richardson and the beginning paragraph
of column 3, there are essentially parallel operations taking
place in Richardson’s circuits such as in representative Figure 1
where the result cache 10 is accessed contemporaneously with the
functioning of the arithmetic circuit 40. If a “hit” occurs in
the result cache 10, the halt signal 60 is issued to stop the
operation in the arithmetic circuit 40.
Thus, even if it would have been obvious to combine the
structure of Sierra to embody an arithmetic circuit in
Richardson, it appears that the feature of determining whether a
first value is present in a cache memory before other operations
are taking place as set forth in independent claim 1 on appeal
would not have been performed. It appears that the combination
would have yielded their contemporaneous access to the cache
memory at the same time that the reciprocal is being determined
according to Sierra’s teachings embodying the arithmetic circuit
as substituted in Richardson from Sierra. Claim 1 is conditional
in that if the first value is found in the cache the truncated
cache operation occurs, but at the same time, the claim requires
that if the first value is not present in the cache memory, a
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