Appeal No. 96-2445
Application 08/289,801
Appellants have appealed to the Board from the examiner's
final rejection of claims 9 through 16, which constitute all
the claims remaining in the application.
Representative independent claim 9, is reproduced below:
9. A method for increased instruction dispatch
efficiency in a superscalar processor system having an
instruction queue for receiving instructions in an application
specified sequential order and loading a group of instructions
in parallel into an associated instruction buffer and an
instruction dispatch unit for dispatching instructions from
said associated instruction buffer to a plurality of execution
units on an opportunistic basis, said method comprising the
steps of:
periodically determining if an instruction within a first
group of instructions within said associated instruction
buffer has been dispatched to one of said plurality of
execution units;
serially shifting remaining instructions within said
associated instruction buffer in said application specified
sequential order in response to a determination that an
instruction within said first group of instructions within
said associated instruction buffer has been dispatched; and
selectively loading said associated instruction buffer
with an additional group of instructions in parallel in said
application specified sequential order utilizing only a
portion of a second group of instructions within said
instruction queue in response to said shifting of said
remaining instructions.
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