Appeal No. 96-2594
Application 08/312,395
The invention pertains to semiconductor devices. More particularly, a semiconductor memory
is provided with stacked capacitor cells and having a structure such that the surface level of the device
has little variation, thus improving miniaturization and integration of the device.
Independent claim 1 is reproduced as follows:
1. A stacked capacitor cell structure for a semiconductor memory device comprising:
a semiconductor substrate;
a field oxide film being selectively formed in a surface region of said semiconductor substrate so
as to define an active region in said surface region of said semiconductor substrate;
a transistor having a diffusion region formed in said active region;
a first interlayer insulator overlying both said transistor and said field oxide film, said first
interlayer insulator having a contact hole with a diameter, said contact hole exposing a part of said
diffusion region of said transistor;
a second interlayer insulator overlying said first interlayer insulator, said second interlayer
insulator both having a through hole with a larger diameter than said diameter of said contact hole and
having a greater thickness than said first interlayer insulator and said field oxide film, said through hole
thereby exposing a part of said first interlayer insulator around said contact hole;
a stacked capacitor formed within said through hole formed in said second interlayer insulator,
said stacked capacitor comprising a storage electrode formed in contact with said part of said diffusion
region of said transistor via said through hole and said contact hole in which a capacitive insulation film
overlying said storage electrode and an opposite electrode overlying said capacitive insulation film; and
a third interlayer insulator overlying both said stacked capacitor and said second interlayer
insulator.
2
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