Appeal No. 1996-3095
Application 08/346,311
which constitute all of the pending claims in the application before us.
BACKGROUND
The subject matter on appeal is directed to a DRAM parity protection scheme which uses
horizontal and vertical parity bits to detect and correct soft errors in the memory (see specification,
page 1). As stated by appellants at pages 1 to 2 of the specification, soft errors caused by alpha
particles emitted from within the DRAM can change bit data from one logic level (e.g., "1") to another
(e.g., "0"). By performing parity checking using parity bits which are located in a protected memory
space which is a subset of, and separate from, the total DRAM space used for data storage, appellants
have overcome difficulties of prior art parity protection schemes. Appellants’ DRAM parity protection
scheme of claims 1 to 4 on appeal enables soft error correction using parity checking which provides
the significant improvement of restarting of the code while avoiding completely reloading the code (see
specification, page 3).
Representative independent claim 1 is reproduced below:
1. A DRAM memory comprising:
a plurality of memory storage cells arranged in an array of rows and columns;
a protected memory space comprising a subset of the rows and the columns of memory storage
cells wherein data and horizontal parity bits for the data are stored, and a vertical parity database
wherein vertical parity bits are stored;
the data stored in the protected memory space being arranged in rows of horizontally
contiguous bytes;
2
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