Ex parte COOPER - Page 4




            Appeal No. 96-3640                                                                           
            Application No. 08/184,794                                                                   


                                            The Prior Art                                                
                        Gage discloses a method and apparatus for removing                               
            the background of a scene of an optical tracking system.  As                                 
            illustrated by the steps 70-88 of Figure 5, an analog video                                  
            signal from a camera is converted to a 6-bit byte digital bit                                
            stream, and top and bottom scanning lines representative of                                  
            the background are stored.  Scanning lines containing target                                 
            data are compared to the stored lines and are converted to a                                 
            serial digital bit stream having a ZERO base line                                            
            representative of the background and variable width ONEs                                     
            representative of the target.  The centroid of the target is                                 
            calculated and utilized to generate a tracking error between                                 
            the centroid and the camera boresight.  See Figure 5, steps                                  
            94, 96.                                                                                      
                               The Rejection under 35 U.S.C. §103                                        
                        Appellant's arguments with respect to the                                        
            independent claims appear at pages 3 and 4 of the brief and                                  
            are as follows:                                                                              
                       Claim 1 includes "... said timing controller                                     
                              generating said image area gate, storage area                              
            gate,       serial register gate signals, a plurality of display                             
                        timing signals, and determining timing relationships                             
                        therebetween in response to said vertical and                                    
                                                   4                                                     





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