Appeal No. 96-4169
Application 08/378,066
wherein the peripheral controller has a core microprocessor
configured to receive at least one interrupt and capable of
operating in a low power mode while awaiting interrupts, and
also has addressable memory space.
On the other hand, Galbraith is concerned with a
completely different problem. In column 1, lines 5-50,
Galbraith
teaches that the problem in the prior art is that electronic
data processing equipment designed to operate with information
data in parallel is generally not compatible with electronic
data processing equipment designed to transmit and receive
information data serially. In column 1, lines 52-63,
Galbraith teaches that their invention overcomes this problem
by providing an electronic asynchronous buffered interface
circuit between the central data processing unit, which
communicates in serially coded ASCII, and a data terminal
comprising a printer and keyboard both of which are designed
to operate with information data in parallel. In column 2,
lines 39-54, Galbraith refers to Figure 1 which shows a
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