Appeal No. 96-4184
Application No. 08/159,346
a data processor bus;
a plurality of N data registers connected to said data
processor bus, said N data registers connected together in a
loop with a most significant bit of one data register
connected to a least significant bit of a sequential data
register, a most significant bit of a last sequential data
register connected to a least significant bit of a first
sequential data register; and
a register selection circuit connected to said N data
registers, said register selection circuit
selecting a specified data register for read access
via said data processor bus in a normal register read mode,
selecting a specified data register for write access
via said data processor bus in a normal register write mode,
and
rotating the bits in each data register within said
loop in a register rotation mode.
The references relied on by the examiner are:
Meltzer 4,368,513 Jan. 11,
1983
Kloker 4,744,043 May 10,
1988
Cornaby 5,410,722 Apr. 25,
1995
(filed Jan. 21,
1993)
Claims 65 through 67 stand rejected under 35 U.S.C. § 103
as being unpatentable over Cornaby in view of Meltzer.
Claim 108 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Cornaby in view of Meltzer and Kloker.
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