Appeal No. 1997-0637
Application 08/265,965
field to store a pointer to the next space in memory for that
chain.” On the other hand, Livay utilizes two separate
locations to store the data and the pointer address, see 212
or 10 and LLT in figures 1 and 2. Livay does disclose that
one read and one write can be done during the same memory
cycle and FIFO memory system is capable of updating the tables
LLT and PT during the same cycle in which a FIFO is accessed,
see column 5, lines 52 to 57. However, the pointer
information is being updated in the tables LLT and PT, and the
data is being accessed elsewhere (i.e., another location) in
FIFO. Therefore, we conclude that Livay does not anticipate
claim 1. Consequently, we do not sustain the anticipation
rejection of claim 1 over Livay.
The other independent claims, 8, 15 and 20, each have a
limitation which corresponds to the limitation discussed
above, namely: “fourth means for writing . . . data and . . .
start address to said current location in a single write
cycle” (claim 8), “means for writing . . . data and said free
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