Appeal No. 1997-1034
Application No. 08/279,135
BACKGROUND
The appellant's invention relates to a memory circuit having varied levels of doping
between the pass gate transistors and the pull-down/up transistors. An understanding of
the invention can be derived from a reading of exemplary claim 1, which is reproduced
below.
1. A memory circuit, comprising:
a flip-flop circuit for storing data having first and second pull down
transistors, a gate of each of said pull down transistors having a first predetermined
conductivity level; and
first and second pass gate transistors coupled to said flip-flop, a gate of
each of said pass gate transistors having a second predetermined conductivity
level less than said first predetermined level wherein data is read from and written
to said flip-flop through said pass gate transistors.
The prior art references of record relied upon by the Examiner in rejecting the
appealed claims are:
Klein et al (Klein) 3,673,471 Jun. 27, 1972
Harari 4,132,904 Jan. 02, 1979
Ichinose et al. (Ichinose) 5,020,029 May 28, 1991
Miyaji 5,070,482 Dec. 03, 1991
Claims 1, 3 and 5 stand rejected under 35 U.S.C. § 103 as being unpatentable
over Miyaji and Klein. Claims 1-6, 15-17, 19 and 20 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Ichinose and Klein. Claim 4 stands rejected under
2
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