Appeal No. 97-1263 Page 2
Application No. 08/219,552
BACKGROUND
The appellants’ invention is a system for interfacing a
plurality of host processors to a plurality of Small Computer
System Interface (SCSI) peripheral devices, i.e., SCSI
targets, via a single SCSI initiator. Status data, i.e.,
ATTENTION DATA, from each target are written to a memory from
which the host processors can read the data. The memory
contains a separate address space for each combination of
processor and target.
Claim 1, which is representative for our purposes,
follows:
1. A system including a small computer system
interface comprising:
a plurality of host processors;
a controller connected to each of said plurality of
host processors, said controller including an
interconnection of only one SCSI initiator, at least
one host adapter, a microprocessor and a memory;
a plurality of SCSI targets with each of said
plurality of SCSI targets connected to said
controller;
said each of said host processors having issuing
and receiving means for issuing separate commands to
designated SCSI targets through said controller and
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Last modified: November 3, 2007