Ex parte TAGUCHI et al. - Page 9




          Appeal No. 97-1694                                                          
          Application 08/351,064                                                      

          circuited), there is, by definition, no current flowing in the              
          bus since there is no current path between the bus and the                  
          supply voltage or between the bus and ground.  This is also                 
          true of the admitted prior art of figure 3; when transistors                
          13 and 14 are OFF, there is no current flowing in the bus.                  
          Appellants have not shown that current flows in the bus of IBM              
          when there is no signal.  Therefore, the rejection of claims                
          40 and 55 is sustained.                                                     


          Claims 41 and 43                                                            
               Claim 41 recites that "a sum of forward direction                      
          threshold voltages of the first and second non-linear elements              
          are greater than a difference between the termination voltage               
          and the voltage carried via the voltage line and lower than                 
          the termination voltage."  Appellants argue (Br10):                         
                    It can be seen from Fig. 3 of the IBM TDB reference               
               that a current flows from the p-channel transistor to the              
               n-channel transistor even when no signal is transmitted                
               via the transfer line.  The graph of Fig. 3 shows a                    
               current flows from the p-channel transistor to the                     
               n-channel transistor even when the voltage described in                
               the horizontal line of the graph is zero.                              
          We do not agree with this reasoning.  Figure 3 is a graph of                
          current in the PMOS or NMOS device versus the voltage at the                

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