Ex parte FUJII et al. - Page 5




               Appeal No. 1997-1696                                                                                                    
               Application 08/180,770                                                                                                  


               suggestions.  In re Sernaker, 702 F.2d 989, 995, 217 USPQ 1, 6 (Fed. Cir. 1983).  We note that                          

               our reviewing court states that "when determining obviousness, the claimed invention should be                          

               considered as a whole; there is no legally recognizable 'heart' of the invention."  Para-Ordnance Mfg.                  

               v. SGS Importers Int'l, Inc., 73 F.3d 1085, 1087, 37 USPQ2d 1237, 1239 (Fed. Cir. 1995), cert.                          

               denied, 519 U.S. 822 (1996) citing W. L. Gore & Assoc., Inc. v. Garlock, Inc., 721 F.2d 1540,                           

               1548, 220 USPQ 303, 309 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).                                            

                       On pages 8 through 11 and 15 of the brief, Appellants argue in regard to claims 20 through 24,                  

               31, 32 and 36 through 39 that neither Suzuki nor the admitted prior art figures 1 and 2 teaches or                      

               suggests that the specific potential applied to the first region has a potential which is lower and has a               

               greater magnitude than the potential of the input signal V .  In regard to claims 25 through 28, 30, 33,                
                                                                            in                                                         
               34, 40 through 43 and 45, Appellants argue on pages 12 through 15 of the brief  that neither Suzuki nor                 

               the prior art figures 1 and 2 teaches or suggests applying a first power source potential to the first                  

               region and to the second region, applying the reference signal V  to the first current terminal of the first            
                                                                                   ref                                                 
               input field effect transistor, applying the input signal V  to the first current terminal of the second input           
                                                                          in                                                           
               field effect transistor, and applying to the third region a power source potential higher than the first                

               power source potential under a test condition.                                                                          






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