Appeal No. 1997-2587
Application No. 08/078,864
OPINION
We will sustain the rejection of claim 4 under 35 U.S.C.
§ 102(b) as anticipated by Green and the rejection of claim 21
under 35 U.S.C. § 103 as unpatentable over Green. However, we
will not sustain the rejection of any other claim based on the
evidence provided by the applied references.
Turning first to claim 4, the examiner indicates that the
“addressable logic circuitry at each pixel circuit element
location” is met by counter 2 at each pixel in Green. The
examiner also indicates that common load data bus means, 3, of
Green meets the claimed “common bus means.”
Appellants take issue with the examiner’s position,
arguing that Green does not disclose the claimed addressable
logic circuitry or the common bus means. Rather than a common
bus that transmits both data and an address so that each
pixel’s logic circuitry can accept the data directed towards
it, Green, as argued by appellants at pages 4-5 of the
principal brief, “relies on a specific sequence of data
shifted over a common load data bus, and necessarily places
the data in a time sequence determined by the location of the
pixel, because each pixel location relies upon the previous
4
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