Appeal No. 1997-0556
Application No. 08/286,265
OPINION
In reaching our decision in this appeal, we have given careful consideration to the
appellants’ specification and claims, to the applied prior art references, and to the
respective positions articulated by appellants and the examiner. As a consequence of our
review, we make the determinations which follow.
Appellants argue that the two references are fundamentally different and
incompatible. (See brief at page 9.) We agree with appellants to the extent that the
Rosich reference emphasizes the teaching concerning the main memory read procedure
and briefly addresses the updating of the cache memory while the other reference to
Patterson is only concerned with teaching the narrow area concerning the cache operation.
In our view, the examiner has not provided a motivation in the individual references, a
statement of the general knowledge in the art or a convincing line of reasoning why one
skilled artisan would have been motivated to combine the distinct teachings.
Appellants argue that the present invention solves a problem in the art con-cerning
the merging of buffer data with cache array data for read operations without causing
delays. Appellants’ solution involves adding circuitry to the cache to substitute the buffer
data for the cache array data if the data are located in the buffer. (See brief
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