Appeal No. 1997-0562
Application No. 08/255,130
BACKGROUND
The appellants’ invention relates to a method and system for nonsequential
instruction dispatch and execution in a superscalar processor system. An understanding
of the invention can be derived from a reading of exemplary claim 1, which is reproduced
below.
1. A method for enhanced instruction dispatch efficiency in a superscalar processor
system which can fetch an application specified ordered sequence of scalar instructions
and simultaneously dispatch a group of said scalar instructions to a plurality of execution
units, said method comprising the steps of:
dispatching selected ones of said group of scalar instructions to selected ones of
said plurality of execution units on an opportunistic basis;
nonsequentially executing selected ones of said group of scalar instructions within
said plurality of execution units;
storing results of execution of each of said dispatched scalar instructions in
intermediate storage buffers within said superscalar processor system;
maintaining an indication of completion of execution of each of said dispatched
scalar instructions in a separate completion buffer; and
controlling the transferring of results of execution of selected ones of said
dispatched scalar instructions from said intermediate storage buffers to selected general
purpose registers in an order consistent with said application specified ordered sequence
in response to said maintained indication of completion of execution of said selected ones
of said dispatched scalar instructions within said separate completion buffer.
2
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