Appeal No. 1997-0605
Application No. 08/551,981
BACKGROUND
The appellant's invention relates to a dual threshold digital receiver with large noise
margin. An understanding of the invention can be derived from a reading of exemplary claim
13, which is reproduced below.
13. A method of converting one set of input signals of 0 and 3.3 volts, and another set of
input signals of 0 and 2.5 volts into one set of output signals of 0 and 3.3 volts such that noise
margin is maximized; said method being performed by a circuit having first and second
transistors in series from a first bus at 3.3 volts to a second bus at 0 volts, and having third
and fourth transistors in series from an output node between said first and second transistors
to said second bus; said method including the steps of:
receiving said one set of input signals on an input which is coupled to respective gates
in said first, second, and third transistors while a control signal of 0 volts is applied to a gate
in said fourth transistor; and subsequently receiving said another set of input signals on said
input while a control signal of 3.3 volts is applied to said gate in said fourth transistor;
selecting said transistors with respective turn-on voltages such that: a) said first and
second transistors enter a fully-on state and said fourth transistor enters a fully-off state when
said input signal is halfway to 3.3 volts and said control signal is at 0 volts; and, b) said first
and fourth transistors enter said fully-on state and said second and third transistors enter a
partially-on state when said input signal is half-way to said 2.5 volts and said control signal is
at 3.3 volts;
further selecting said transistors with respective channel lengths and widths such that:
a) said first, second and fourth transistors have respective channel resistances in said fully-on
state of R1 , R2 and R4 ; b) said second and third transistors have respective channelON ON ON
resistances in said partially-on state of R2 and R3 , both of which vary exponentially withPON PON
gate voltage; and, c)R2 equals R1 , and R2ON ON PONin parallel with R3 PONplus R4 equalsON
R1 .
ON
2
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