Appeal No. 1997-0706
Application No. 08/040,528
Digital Data Sys., Inc., 730 F.2d 1440, 1444, 221 USPQ 385,
388 (Fed. Cir.); cert. dismissed, 468 U.S. 1228 (1984); W.L.
Gore & Assocs. v. Garlock, Inc., 721 F.2d 1540, 1554, 220 USPQ
303, 313 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
With respect to independent claims 1 and 7, the Examiner,
at pages 3 and 4 of the Answer, attempts to read the various
claim limitations on the Chuang reference. In particular, the
Examiner points to the chip socket 10 and control logic
circuitry 14 illustrated in Chuang’s Figure 2.
In response, Appellant’s primary argument (Reply Brief,
page 2) centers on the contention that Chuang fails to
disclose the determination of a particular chip type installed
in the chip socket “by reading a predetermined memory location
of a chip installed in said chip socket” as claimed. After
careful review of the Chuang reference in light of the
arguments of record, we are in agreement with Appellant’s
position as stated in the Reply Brief.
We agree with Appellant that, while Chuang utilizes
a signal (MP#) emanating from a particular socket pin, i.e.,
pin 31, for chip type identification, there is no indication
from the disclosure of Chuang that this signal is associated
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