Appeal No. 1997-3688
Application 08/113,887
27. A method for forming a semiconductor device, comprising the steps of:
providing a semiconductor body;
forming a first silicon nitride layer over said semiconductor body;
forming a polysilicon layer on said first silicon nitride layer;
forming a second silicon nitride layer on said polysilicon layer;
removing portion of said second silicon nitride layer, said polysilicon layer, and said first
silicon nitride layer to define an active moat region and to expose an inverse moat region;
forming a silicon nitride sidewall seal abutting said first and second silicon nitride layers
and said polysilicon layer on said active moat region; and
forming a trench with a sidewall and a bottom in said semiconductor body adjacent to said
silicon nitride sidewall seal.
The Examiner relies on the following references:
Bryant et al. (Bryant) 4,981,813 Jan. 1, 1991
Japan Kokai (Saito) 62-71247 Apr. 1, 1987
Japan Kokai (Koto) 63-137457 June 9, 1988
Wolf et al. (Wolf), “Silicon Processing for the VLSI Era,” Process Technology, Vol. 1,
Lattice Press, pp. 523-29 (1986)
Claims 27, 31 and 32 stand rejected under 35 U.S.C. § 103 as being unpatentable over
the combination of Saito, Koto, Bryant and Wolf.
Rather than reiterate the arguments of Appellant and the Examiner, reference is made to
the brief and answer for the respective details thereof.
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