Ex parte GOEDKEN et al. - Page 7




              Appeal No. 1997-3839                                                                                        
              Application No. 08/120,144                                                                                  


                     Again, the examiner has not provided a clear correspondence of the specific                          
              portion of Nagasawa which is being relied upon to teach the claimed invention.  Therefore,                  
              we review Nagasawa with the limited guidance of the examiner.  From our review of                           
              Nagasawa, we find that Nagasawa teaches the evaluation of the volatile memory and                           
              determining the type of reset, but Nagasawa teaches only initializing the memory for a                      
              power-on reset.  (See Nagasawa at col. 3.)  Nagasawa states:                                                
                            After a reset start by the application of the power current, the CPU 1                        
                     monitors the Q output signal level of the FF 11 through the I/O unit 4.  If the Q                    
                     output signal is at the low level as shown in FIG. 2C, the CPU 1 judges that                         
                     the power-on reset should be done, and performs the initial setting such as a                        
                     RAM clear operation.  If, on the other hand, the output signal level of the Q                        
                     output signal of FF 11 is high, a normal back-up power voltage is applied                            
                     and the backup operation of the time of power down is performed, and                                 
                     further the CPU 1 judges that a reset of the release from the power down                             
                     mode should be effected, and the CPU 1 operates so as not to perform the                             
                     initial setting of the RAM data.  In FIG. 2F, the character a indicates the                          
                     operation of the level detection of the FF 11, and the character b indicates                         
                     the operation of the initialization of the RAM.  In the case of the initialization                   
                     of the RAM, the FF 11 is set by means of the output signal from the I/O unit 4                       
                     so as to provide for the next cut-off of the system power supply.  (Column 3,                        
                     lines 12-31) (Emphasis added.)                                                                       
              Nagasawa later states that:                                                                                 
                            The system of the present invention is based on the difference                                
                     between this irregularity of data in the time of normal power-on resetting and                       
                     the preservation of the data after the "power down mode", and characterized                          
                     by storing the check code CD2 [sic] and/or a particular pattern code PC  in                          
                                                                                                 3                        
                     the RAM 3.  Thus, it becomes possible to determine the type of reset                                 
                     operation by detecting the check code CD  or the                                                     
                                                                  2                                                       



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