Appeal No. 1997-4051 Page 4
Application No. 08/479,245
a cache memory for said main memory system, said
cache memory including a cache controller coupled to
receive said second control signal, said cache
controller initially operating said cache memory as
a "write-back cache”, said cache controller
providing, in response to said second control
signal, an interrupt signal to said central
processing unit, thereby causing said central
processing unit to execute a service routine in
response to said interrupt signal, said service
routine causing said central processing unit to
provide a third control signal to said cache
controller, whereupon said cache controller either
disables said cache memory or operates said cache
memory as a write-through cache, in response to said
third control signal.
The reference relied on in rejecting the claims follows:
Shimoi 5,007,027 Apr. 9, 1991.
Claims 1-8 stand rejected under 35 U.S.C. § 103 as
obvious over Shimoi. Rather than repeat the arguments of the
appellant or examiner in toto, we refer the reader to the
briefs and answer for the respective details thereof.
OPINION
In reaching our decision in this appeal, we considered
the subject matter on appeal and the rejection advanced by
the examiner. Furthermore, we duly considered the arguments
and evidence of the appellant and examiner. After considering
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