Ex parte TERANE - Page 2



          Appeal No. 1998-0496                                                        
          Application 08/356,966                                                      



          The disclosed invention pertains to a method and apparatus                  
          for processing signals.  The invention has particular disclosed             
          utility in the decoding of variable length Huffman codes for use            
          in performing transformations in the restoration of received                
          image data.                                                                 
          Representative claim 1 is reproduced as follows:                            
               1.  A signal processing device for processing an input                 
          signal including a plurality of first digits and a plurality of             
          second digits, wherein the plurality of first digits indicate a             
          run length of a single first value, and wherein the plurality of            
          second digits include at least one second value other than said             
          first value, said signal processing device comprising:                      
               (a) an address generator comprising:                                   
                    (a-1) a first input for sequentially receiving a run              
          length indicative of a number of contiguous first values in said            
          input signal;                                                               
                    (a-2) a second input for sequentially receiving said              
          second digits;                                                              
                    (a-3) a first output for sequentially outputting a                
          first address updated by a value of said run length plus one; and           
                    (a-4) a second output for sequentially outputting said            
          second digits in synchronism with a first address, and                      
               (b) a signal processor for performing a predetermined signal           
          processing upon said first address and said second digits to                
          output an array of output signals.                                          
          The examiner relies on the following references:                            
          Saito et al. (Saito)          5,184,229          Feb. 2, 1993               
          Fukuda et al. (Fukuda)        5,416,854          May 16, 1995               
          (filed July 30, 1991)                                                       

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