Appeal No. 1998-0524
Application No. 08/522,067
In this manner, these processors can more efficiently process
multimedia applications.
With reference to the claimed invention, execution of a
single packed data instruction causes at least two independent
multiply-add operations on packed data inputs. See for
example, Table 3a in Appellants’ specification.
Representative independent claim 28 is reproduced as
follows:
28. In a computer system, a method for manipulating a
first packed data and a second packed data responsive to the
execution of a single instruction, said first packed data
including A A A , and A as data elements, said second packed1, 2, 3 4
data including B , B , B , and B as data elements, said method1 2 3 4
comprising the steps of:
multiplying together A1 [sic] and B1 [sic] to generate a
first intermediate result;
multiplying together A2 [sic] and B2 [sic] to generate a
second intermediate result;
multiplying together A3 [sic] and B3 [sic] to generate a
third intermediate result; and
multiplying together A4 [sic] and B4 [sic] to generate a
fourth intermediate result;
performing in parallel the following steps:
adding together said first intermediate result and said
second intermediate result to generate a first data element in
a third packed data; and
-3-3
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