Appeal No. 1998-0723
Application 08/570,851
The disclosed invention pertains to a computer
implemented method of design verification for asymmetric phase
shift mask layouts. The invention is used to efficiently
indicate to a designer whether a basic phase shifted mask
design is met throughout the entire chip design.
Representative claim 1 is reproduced as follows:
1. A computer implemented method of design verification
for asymmetric phase shift mask layouts comprising the steps
of:
isolating “critical” features in a design based on
criteria that were applied in an original design routine;
expanding the designed phase regions by the width of the
largest “critical” features to give shapes A;
locating all overlaps of the expanded phase regions to
identify shapes B;
isolating any defective “critical” features by first
subtracting the overlap region shapes B from the expanded
phase region shapes A to produce phase regions shapes C, and
then subtracting the remaining phase regions shapes C from the
isolated “critical” features, leaving only “critical” features
that were either covered by the overlap of two phase regions
or were not covered by a phase region at all; and
presenting to a designer design conflicts characterized
as “critical” features that either have a phase region on both
sides or have no adjacent phase region at all.
The examiner relies on the following references:
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