Appeal No. 1998-1096
Application No. 08/415,399
can cause charge bursts and signal upsets. Appellants
indicate at pages 2 and 3 of the specification that this
protection takes the form of a thermal neutron absorbing layer
provided either on the integrated circuit itself, or included
on the walls of the integrated circuit container.
Claim 5 is illustrative of the invention and reads as
follows:
5. An integrated circuit, comprising:
(a) a substrate containing devices at a surface;
(b) a layer containing thermal neutron absorbers
over said surface, said layer not packaging material,
wherein said thermal neutron absorbers reduce
incident thermal neutrons by a factor of about 2 or more.
The Examiner relies on the following prior art:
Cannella et al. (Cannella) 4,691,243 Sep. 01, 1987
Sugawara 64-289521 Jan. 31, 1989
(Published Japanese Kokai Patent Application)
Claims 8-10 stand finally rejected under the second
paragraph of 35 U.S.C. § 112 as being indefinite for failure
to particularly point out and distinctly claim the invention.
1A copy of a translation provided by the U.S. Patent &
Trademark Office, March 1998, is included and relied upon for
this decision.
2
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