Appeal No. 1998-2596
Application 08/522,222
to an on-chip memory based on predictions as to what
instructions a computer will probably execute after the
instruction in progress has been completed. The invention is
primarily concerned with the manner of caching prefetched
instructions which are not subsequently referenced by the
computer.
Representative claim 1 is reproduced as follows:
1. An instruction prefetching method wherein instruction
blocks prefetched in accordance with an instruction prefetch
mechanism, but not referenced by a central processing unit are
stored in an on-chip memory without being discarded upon
replacing them by new ones in a prefetch buffer so that they
are to be used for memory reference at later times.
The examiner relies on the following reference:
Jouppi et al. (Jouppi) 5,261,066 Nov. 09, 1993
Claims 1-27 stand rejected under 35 U.S.C. § 103. As
evidence of obviousness the examiner offers Jouppi taken
alone.
Rather than repeat the arguments of appellants or the
examiner, we make reference to the briefs and the answer for
the respective details thereof.
OPINION
We have carefully considered the subject matter on
2
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