Appeal No. 1997-3843
Application No. 08/221,030
BACKGROUND
The appellant's invention relates to a first order tuning circuit for a phase-locked loop.
1
An understanding of the invention can be derived from a reading of exemplary claim 1 ,
which is reproduced below.
1. A phase-locked loop circuit, comprising:
a clock input for receiving a data clock signal having an input frequency;
a voltage controlled oscillator for generating a VCO output clock signal having an
output frequency controlled by a voltage across a capacitor;
a tuning circuit for generating first and second control signals in response to the
input frequency of the data clock signal and the output frequency of the VCO output clock
signal; and
means for applying both the first and second control signals to the capacitor to
apply and remove charge to the capacitor proportional to the phase overlap between the
first and second control signals.
The prior art references of record relied upon by the examiner in rejecting the appealed
claims are:
Nishita et al. (Nishita) 5,052,022 Sep. 24, 1991
Pearson 5,276,712 Jan. 04, 1994
The examiner indicated in the answer at page 2 that the amendment after final rejection, filed on1
Feb. 27, 1997, has been entered. We note that this amendment was actually filed on Feb. 12, 1997 with
the Appeal Brief and has not been officially entered in the file wrapper. No Advisory action was mailed in
response to the amendment. Since the examiner has expressly indicated that the amendment was
entered, we consider claim 1 as amended.
2
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