Ex parte CAROBOLANTE - Page 4




          Appeal No. 1998-0295                                                        
          Application No. 08/202,828                                                  


               The obviousness rejection of claims 1 through 17, 19 and               
          21 through 24 is reversed.                                                  
               The examiner recognizes (final rejection, page 3) that                 
          the admitted prior art does not teach “discharging the                      
          capacitor, or integrstor [sic, integrator], during ‘off’                    
          times.”  According to the examiner, “Rhodes teaches such a                  
          discharging technique.”  Based upon the teachings of Rhodes,                
          the examiner concludes (final rejection, page 3) that:                      
               One of ordinary skill in the art would have known to                   
               null the capacitor as Rhodes teaches to start at                       
               this zero level so as to fire the capacitor at known                   
               and constant times.  One could not predict when the                    
               capacitor would fire if there was an undetermined                      
               amount of charge remaining on the capacitor.                           
               As the title of Rhodes’ integrator invention indicates,                
          Rhodes is concerned with fast discharge of a capacitor when an              
          input signal to the integrator changes polarity.  A positive                
          input signal on lead 10 to the integrator is inverted by                    
          amplifiers 14 and 18 (Figure 1).  The negative output signal                
          from inverter 18 charges capacitor 52, and the negative output              
          from inverter 14 activates switch 46, but not switch 36                     
          (column 2, lines 34 through 49).  During this state,                        
          integration with capacitor 52 and integrating amplifier 18                  

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