Appeal No. 1998-1800
Application No. 08/430,453
and 9, the Examiner, as the basis for the obviousness
rejection, proposes to modify the disclosure of Olson which
provides, during a “split-mode” operation, for updating of
cache memory during a read operation even when reading from
the cache is inhibited.
The Examiner, while recognizing that Olson does not disclose
the updating of cache memory during write operations to
noncacheable locations as required by the language of the
appealed claims, nevertheless offers the following conclusion
(Answer, pages 3 and 4):
In as much as main memory writes will change
main memory data, which, if not accounted for,
will create a coherency problem if cached data
corresponding to the same memory address were
not also updated, it would have been obvious
at the time the invention was made to a person
having ordinary skill in the art to which said
subject matter pertains to have made the device
taught by the Olson reference to also update
memory writes in the cache while in split mode
so that, should a write occur to a non-cacheable
location that has been cached, the cache will be
up-to-date and therefore be able to immediately
supply accurate data as soon as the CPU changes
the cacheability status of the given address, as
noted to be desirable.
7
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