Appeal No. 1998-1914
Application No. 08/528,130
The operation of the “channelizer” and “voting logic” functional blocks shown in
Figure 6 are explained in the reference prior to the column 8 teaching pointed out in the
rejection. As explained principally at column 5, lines 23-61 and column 6, lines 27-68,
latch 72 (Fig. 4A) of a voting logic circuit is set if that particular filter in an odd-numbered
channel has the output of greatest value in the odd-numbered group of channels. An
identical test is performed for the even-numbered channels, and the latch representing the
filter having the output of greatest value in the even-numbered channel group is also set.
The first greatest value circuit 68 provides an output signal 70 equal to the magnitude of
the input channel of the odd-numbered channels having the greatest magnitude. Similarly,
second greatest value circuit 78 provides an output value 79 corresponding to the
maximum output signal from the even-numbered channels.
As shown in Figure 4B, the output signals 70 and 79 are connected to a difference
circuit 108, with the difference between the signals directed to computer 24 via A/D
converter 110. The difference signal, as shown in Figure 7, is used by the computer, along
with the other input signals, in determining where the signal lies in the filter passband
having the greatest output signal.
Thus, even if there is a comparison of the magnitude of the RF signal through the
use of wide band discriminator 128 (Fig. 6), the comparison is with a difference signal
formed from the greatest value present in two respective groups of filters. There is no
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