Appeal No. 1998-2093
Application No. 08/303,809
computer is ready to extract data from the mapped portion,” which paraphrases paragraph
“iii” of claim 13.
Appellants, at pages 13 and 14 of the Brief, argue that Yamaoka fails to disclose
generation of the claimed first, second and third signals, and further does not teach the
“sequence” set forth in the claims. The examiner responds (Answer at 5) that the examiner
“does not see any particular sequence mentioned in the claims.”
We note that claim 13 is not a process claim. However, as appellants emphasize,
the claim does set forth an ordered progression of signals and associated responses,
including transmission and reception of a “first signal,” a “second signal,” and a “third
signal.” For example, paragraph “iv” sets forth computer readable program code means
“for instructing said provider computer after receipt of said first signal to transfer said data
to said mapped portion at said address in said shared memory” (emphasis added).
Paragraph “iii” sets forth computer readable program means “for transmitting a first signal
to said provider computer that said consumer computer is ready to receive and extract
data from said shared memory” (emphasis added). Placing the elements of paragraph
“iv” before the elements of paragraph “iii” in the statement of the rejection may represent
giving no weight to the sequence related to transmission and reception of the “first signal.”
However, the requirements of the claim cannot be ignored.
In any event, we agree with appellants that the rejection does not show that
Yamaoka generates signals as presently claimed. The Final Rejection refers (page 3) to
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