Appeal No. 1998-2956
Application No. 08/709,964
BACKGROUND
The appellants’ invention relates to a high density dynamic random access memory
cell structure having a polysilicon pillar capacitor. An understanding of the invention can be
derived from a reading of exemplary claim 20, which is reproduced below.
20. An array of pillar-shaped stacked storage capacitors on a semiconductor
substrate, comprising of:
a semiconductor substrate having field oxide areas surrounded and electrically
isolated device areas, said device areas having semiconductor devices formed, in part,
from a patterned first polysilicon layer, and said devices areas also having device contact
areas;
a first insulating layer on said substrate and over said patterned first polysilicon
layer,
pillar-shaped capacitor bottom electrodes aligned within and electrically contacting
said device contact areas, and further having vertical sidewalls and extending upward over
said device contact areas, said pillar-shaped bottom electrodes formed by filling with a
second polysilicon layer node contact openings formed in a second insulating layer
deposited over said first insulating layer, and then oxidizing and removing said oxidized
portion of said second polysilicon layer and said second insulating layer, thereby providing
free standing pillar-shaped bottom electrodes;
a capacitor interelectrode dielectric layer on said bottom electrodes;
a patterned third polysilicon layer on said capacitor interelectrode dielectric layer
forming top capacitor electrodes, and thereby providing said pillar-shaped stacked
storage capacitors.
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