Appeal No. 1998-2982
Application No. 08/582,716
BACKGROUND
The invention is directed to an incrementer circuit. Claim 1 is reproduced below.
1. An incrementing circuit comprising:
an input latch for receiving a pulsed input data and outputting a static
complement of the pulsed input data, the pulsed input data representing a number
to be incremented;
a carry-lookahead circuit, coupled to receive said static complement of the
pulsed input data, said carry-lookahead circuit for generating a carry signal from the
number to be incremented; and
a summing circuit coupled to receive the carry signals from the carry-
lookahead circuit and the pulsed input data representing the number to be
incremented, said summing circuit for summing said carry signals and said pulsed
input data and producing a pulsed output representing a sum.
The examiner relies on the following references:
Renfro et al. (Renfro) 5,345,110 Sep. 6, 1994
Jagini 5,384,724 Jan. 24, 1995
Claims 1-7, 10, and 11 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Jagini and Renfro.
We refer to the Final Rejection (Paper No. 7) and the Examiner's Answer (Paper
No. 12) for a statement of the examiner's position and to the Brief (Paper No. 11) and the
Reply Brief (Paper No. 13) for appellants’ position with respect to the claims which stand
rejected.
-2-
Page: Previous 1 2 3 4 5 6 Next
Last modified: November 3, 2007