Appeal No. 1998-3331 Page 3
Application No. 08/852,842
DSP’s program memory 202 are physically separate, residing on
separate chips, the program memory space is set up so that the
addresses of the auxiliary DSP’s program memory fall within
the memory address space of the main DSP. Consequently, the
main DSP can write not only to the data memory but can also
write to the auxiliary DSP’s program memory 202. In contrast,
the auxiliary DSP reads instructions only from its own program
memory 202. Sharing the data memory and mapping the auxiliary
DSP’s program memory to the main DSP’s program memory reduce
communication bottlenecks.
Claim 1, which is representative for our purposes,
follows:
1. A multiprocessor computer system,
comprising:
a main digital signal processor (DSP);
at least one auxiliary DSP interacting with said
main DSP for executing digital signal processing
operations;
a data memory shared by said main DSP and one or
more auxiliary DSPs,
a main DSP program memory storing program data of
said main DSP and processing instructions to be executed
by said auxiliary DSP; and
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