Appeal No. 1998-3409
Application No. 08/525,152
that Park teaches that delay data is maintained internally within the microcomputer 10b
and that the delay data is neither output to the integrator circuit 10c nor to the mono-multi
circuit 14. We agree with appellant that Park does not teach or suggest “a controller for
supplying the delay data and the shift command signal of the head switching point of time
for each head to the head switching signal generator according to the output of the format
detector” as recited in claim 1. The basic problem is that the examiner is relying on
essentially the same structure to provide both claim limitations, yet the examiner does not
clearly explain how the reference meets the limitations as recited in claim 1. For example,
the examiner maintains that the “delay data and shift command signal (output 10c and 14)”
are output from “format detector 10(b)”. Later the examiner maintains that “controller for
supplying the delay data and shift command signal (10, 10c)” is taught by Park. (See
answer at page 3.) Here, the examiner relies upon different teachings within the reference
for the same information where one is the overall automatic mono-multi signal control
circuit 10, and the other is a sub-unit 10c within the automatic mono-multi signal control
circuit 10. The examiner then maintains that the “signal outputted from 14 is being
interpreted as the delay data and shift command signal. In col. 6 lines 47-53, Park
describes how the output from 14 causes the head switching signal to rise from a low state
to a high state.
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