Appeal No. 1999-0528
Application 08/472,770
Finally, in response to appellants' third argument that Matick's memory array is not
divided into a plurality of blocks as claim 19 requires, the examiner has asserted that it
does and indicates at page 5 of the answer that the claimed “blocks” correspond to plural
banks 1 through 4 shown in figure 2 or all of the 32 chips comprising a single bank
represented in this figure. It is also indicated at column 4, lines 47 through 49 of Matick
that “[t]he slaves on the various banks will normally be loaded with the desired working set
blocks being accessed by the CPU.” Therefore, in view of the foregoing arguments
embellishing those positions set forth by the examiner in the final rejection and answer, we
sustain the rejection of representative claim 19 as being anticipated by Matick under 35
U.S.C. § 102.
We turn next to the rejection of claims 19, 21 and 22 under 35 U.S.C. § 103 as
being obvious over Ward. In considering the teachings and showings of Ward from our
study of it, we disagree with appellants' arguments presented as to this rejection at pages
13 through 15 of the principal brief on appeal. We agree with appellants'
assessment that Ward appears to show but does not appear to discuss that the DRAM
array comprising the main memory of figure 1 of this reference is divided into plural or four
columns or blocks where there are plural chips 14 comprising the entire bank 12.
We disagree with appellants' assertion that the artisan would recognize that each
row buffer 16 has a size corresponding to the size of the single DRAM block and therefore
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