Appeal No. 1999-1133
Application No. 08/766,199
wherein a via is formed through an insulating layer to a first metal layer, the sidewalls and exposed metal
bottom are cleaned with a nitrogen-containing plasma, a liner is formed on the via sidewall and bottom
and the via is then filled with a second metal.
Independent claim 5 is reproduced as follows:
5. A method of forming an interconnect, comprising the steps of:
(a) forming a via through an insulating layer to a first metal layer over a substrate;
(b) clean the via sidewalls and exposed first metal bottom with a nitrogen-containing
plasma;
(c) form a liner on the via sidewall and bottom; and
(d) fill the via with a second metal.
The examiner relies on the following references:
Ohtsuka et al. (Ohtsuka) 5,244,535 Sep. 14, 1993
Mizobuchi K. et al., “Application of Force Fill Al-Plug Technology to 64Mb DRAM and 0.35
Fm Logic,” Symposium on VLSI Technology Digest of Technical Papers, 1995, pp. 45-46.
Claims 5 and 6 stand rejected under 35 U.S.C. 102(b) as anticipated by Ohtsuka. Claim 7 stands
rejected under 35 U.S.C. 103 as unpatentable over Ohtsuka and Mizobuchi (abstract only).
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