Ex Parte KAO - Page 2



          Appeal No. 1999-2295                                                        
          Application No. 08/418,797                                                  

          first processor including a first cache configured to store a               
          head pointer of the buffer queue and a second processor including           
          a second cache configured to store a tail pointer of the buffer             
          queue.  Appellant asserts at pages 8 and 9 of the specification             
          that the caches are made independent of each other, thereby                 
          eliminating the need for a shared memory for storing head and               
          tail pointers.                                                              
               Claim 1 is illustrative of the invention and reads as                  
          follows:                                                                    
               1.  A service module, comprising:                                      
                    a buffer queue that stores a data queue, the                      
               buffer queue comprising a plurality of buffers being                   
               linked to one another as a linked list using next                      
               pointers;                                                              
                    a first processor including a first cache coupled                 
               to the buffer queue; and                                               
                    a second processor including a second cache                       
               coupled to the buffer queue,                                           
                    wherein the first processor is configured to store                
               a head pointer of the buffer queue in the first cache                  
               and the second processor is configured to store a tail                 
               pointer of the buffer queue in the second cache, the                   
               first cache being independent of the second cache.                     




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