Appeal No. 1999-2570
Application No. 08/923,218
BACKGROUND
The appellants’ invention relates to a stress reduction feature for 2 leads-over-chip
(LOC) configuration lead frame. The invention provides an enlarged space between the
lower surface of the lead and the active surface of the semiconductor to provide stress
relief and flow of filler material therein. An understanding of the invention can be derived
from a reading of exemplary claim 1, which is reproduced below.
1. A semiconductor die assembly encapsulated in plastic having filler material therein
having a particle size distribution and an average particle size diameter
within the particle size distribution during an encapsulation process in a mold, said die
assembly comprising:
a semiconductor die having an active surface and a plurality of sides;
at least one adhesive segment having an outer edge and adhering to a portion of
said active surface of said semiconductor die; and
a lead frame including a plurality of lead members, at least one lead member of the
plurality of lead members having a lead end portion connected to a portion of
the lead frame, having a length, having a thickness, and having a free end
portion extending over a portion of said active surface of said die, said at
least one lead member including a stress relief portion formed in said at
least one lead member of said plurality of lead members, said stress relief
portion extending over a portion of said active surface of said die, extending
along a portion of the length of said at least one lead member at a location
between said free end portion and said lead end portion and extending
partially through the thickness of said at least one lead member, said stress
relief portion formed in said at least one lead member extending along the
length of the at least one lead member from a location proximate the outer
edge of said at least one adhesive segment to a location proximate a side
of said plurality of sides of said semiconductor die, said stress relief portion
providing an enlarged space between a lower surface of said at least one
lead member and a portion of the active surface of said semiconductor die,
2
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